Dissemination Workshop
Monday 19 September 2022


Smart Power Technologies and Applications

(Room - Aula 1D) Half day


Andrea Natale Tallarico (University of Bologna, IT)

Andrea Natale Tallarico is senior assistant professor at the Department of Electrical, Electronic, and Information Engineering "Guglielmo Marconi" at the University of Bologna. His main research interests include the characterization and modeling of the silicon and wide bandgap (GaN and SiC) power devices reliability.


R3-PowerUP is pushing through a new generation of 300mm Pilot Line Facility for Smart Power microelectronic technology in Europe, which will enable innovative and competitive solutions for energy saving and CO2 reduction, as well as sustainable environment through electric mobility and industrial power efficiency. Since the project is truly multi-disciplinary, the related workshop covers several applications driven solutions for automotive, electric mobility, renewable and smart energy, power conversion and industrial control, Industry 4.0 Fab automatization, and advanced innovative solutions for 3D System-in-Package.

08:30 - 08:40

Welcome and introduction

08:40 - 09:00

Smart Power and Power Discretes Hardware-software co-design on BLDC power driver development

Unprecedented diversity of microcontroller driven high-end electronic devices and applications stimulates the increase of customer expectations for product functionality flexibility and reliability. Advanced integration techniques and controlled product lifetime techniques applied by producers make products hard for service actions, whereas device disassembly before repair is very risky (if only available). Product replacement becomes the most common option instead of the repair for relatively cheap products or modules. Such a situation applies to small electric devices like vehicles, white goods (cookers, hovers, washing machines…) and many more tools and appliances/gadgets periodically appearing nowadays. All of them are exposed for exploitation overload and stress which should be kept under designers control in modules, devices and systems development stage. Following the fact that numerous above mentioned applications do not face voltages over 1kV, the set of Bipolar-CMOS-DMOS (abbr. BCD) technologies is a key branch of ICs development driven by the need to offer more and more complex integrate solutions incorporating diversified/mutual/redundant/complementary functions on the same chip and to guarantee high quality and reliability in all types of application environments. Hardware implementation scenarios available for fully integrated and for hybrid solutions are also discussed.


Grzegorz Janczyk (Lukasiewicz Research Network - Institute of Microelectronics and Photonics (Ł-IMiF)
Research Group of Integrated Circuits and System Design, PL)

Grzegorz Janczyk received  the  M.Sc.  degree  (with  honours)  and  Ph.D.  degree  in  electronic engineering from the Warsaw University of Technology (WUT), Poland in 1999 and 2005 respectively. He was with the Institute of Microelectronics and Optoelectronics, VLSI Engineering and Design Automation Division (IMiO-WUT), at the same university in the period 2005-2018 as an Assistant Professor. In 2006 he joined Institute of Electron Technology (ITE). He is an Assistant Professor in ITE. Since 2012 he is Head of the  Department  of  Integrated  Circuits  and  Systems  in  ITE. Since 2020 je is Leader of the Integrated Circuis and Systems Design Research Group. His  main  Ph.D.  related interests  cover  device modelling  along  with  technological  SOI  fabrication  process  modelling  and  development  of  SOI-MOS transistor models. Multi-domain Verilog modelling using belongs to his professional interests. Statistical yield simulations and mismatch modelling are secondary field of interest. He is also C++ programmer. He is the leader and co-leader of several successfully concluded and ongoing international (European) and domestic (Polish)  projects  like  R3-PowerUp,  REACTION  and  already  concluded:  e-CUBES,  SE2A,  e-BRAINS, CORONA, PARSIMO, SMAC, SESBE, CarrICool, APRIL ParCour projects by FP6, FP7, H2020, ENIAC, ECSEL and domestic funds. Dr Grzegorz Janczyk is the author and co-author of more than 80 technical papers presented in journals and at conferences

09:00 -09:20

Micro-PhotoVoltaic Solar Crysrtal Converter

The University of Seville has developed a series-resonant power converter as a demonstrator for the R3-PowerUp Project. This converter is designed to manage the energy of a photovoltaic panel and inject it into a low-voltage DC bus. The demonstrator core is the X-Spin prototype, which integrates power and signal electronics together in a single device. An iterative design was used to reach the final converter, which is found to be very compact. Regarding the control approach, a mathematical model of the circuit has been has led to a more accurate approximation than the current state of the art. A new Lyapunov-based control algorithm has been developed using this model. In addition to this algorithm, several control techniques were tested on the converter in search of some balance between efficiency, voltage range and power controllability.


Luis Galván García-Pérez (University of Seville, Electronical Engineering Department, ES) 

Luis Galván was born in Seville in Spain, on January 24, 1985. He received the B.E degree in industrial engineering and the M.S. degree in electronics, signal processing and communications from the University of Seville (US), Spain in 2010 and 2015 respectively. He is currently working to obtain the Ph.D. in the same university. He has been working as a researcher in the Department of Electronic Engineering of the University of Seville since 2010. His field of research is power electronics, particularly the balance control of cascade converters and its application for renewable sources and storage systems.

09:20 - 09:40 Innovative 300mm laminar flow thermal mini-batch ALD reactor solution and performance

Atomic layer deposition (ALD) thin films are extensively used among the semi-conductor industry, especially within the 300mm wafer high volume manufacturing sector. From 45nm node to today’s 10nm nodes and beyond, the number of ALD steps for the high-volume manufacturing of semiconductor has increased by a factor 7. Therefore, the needs of producing defect-free and highly uniformed layers are exponentially increasing. Within the R3powerUP framework, we have developed PICOSUN® Sprinter an innovative thermal minibatch laminar flow ALD reactor that aims to match the high-quality film demand together with the high-volume manufacturing needs of the 300mm semiconductor industry. We will present the latest results from deposition of Al2O3 and SiO2 thin films and their characterization. Low process temperature as well as low thermal budget without compromising on the film quality combined with high throughput are the trademark of the presented results.


Tom Blomberg (Picosun Oy, FI) 

Dr. Tom Blomberg works as a senior technology manager in the R&D department of Picosun Oy. He has more than 20 years of experience in developing ALD technology for the semiconductor manufacturing market. He has authored or co-authored around 30 publications on thin film deposition and energy related matters and holds more than 30 US or international patents on different subjects in the ALD and related technologies.

09:40 - 10:00

An embedded system for Non Volatile Memories Validation: HD OTP case of study

In modern technologies there is a strong need to validate each specific NVM IP on silicon before using it in any product. This need consists of extracting yield, functional and electrical parameters from silicon. At the same developing a simple testchip for the IP validation could dramatically increase the test and data analysis complexity. Our approach consists of embedding a microcontroller (ARM based) in the testchip together with the IP to be tested (in our case the High density OTP) in order to develop a standard methodology having the following advantages: i) validate the NVM in a real environment; ii) to use microcontroller as an internal test machine; iii) internal characterization of max freq. and power, different program and read algos; iv) capability of microcontroller SW to be adapted and improved on field. In conclusion this work shows how the silicon validation based on embedded system is a solution to improve, enhance and speed up validation loop of NVM IPs with benefits on final product.


Andrea Veggetti (STMicroelectronics, IT)

Andrea Mario Veggetti received his degree in computer science and microelectronics in 1994 from University of MILAN (IT). He joined STMicroelectronics Central R&D in 1996 starting from digital design and CAD development. Since 2001 he has been working on Testchip development for IPs validation and Ultra Low Power design and test. Starting from 2008 he has been actively working on Soft error characterization due to Ionizing Radiation. In 2011 he started working on Flash memories dsign and validation adopting ARM microcontroller as reference for testchip architecture. He has coauthored more than 10 articles and is the holder several patents in radiation hardening and Ultra Low Power Design.

10:00 - 10:30

Coffee Break 

10:30 - 10:50

Low-power analog circuits for Wake-up Radio in IoT nodes

The topic of this talk is the design of an Analog Front End for a Wake-up Radio using an STMicroelectronics 90-nm BCD technology, developed in the framework of the R3-PowerUP project. The proposed AFE receives OOK-modulated input signals with RF carrier frequencies in the Sub-GHz ISM band and has a power consumption in the order of nanowatts. The main challenge this topic poses is the sensitivity-power trade-off, that is a longer wake-up distance requires a higher power consumption. Two implementations will be presented. Both are clockless and leverage the second-order non-linearities of a MOSFET in subthreshold for envelope extraction. The first and second prototypes both include an active Envelope Detector, a band-pass and a low-pass one, respectively. The first implementation is temperature-compensated by means of a dedicated block.x


Alessia Maria Elgani (ARCES-University of Bologna, IT)

Alessia M. Elgani earned a M.Sc. in Microelectronics from the University of Pavia, Italy in 2016. Over the course of 2016 and 2017, she carried out internships at Texas Instruments and ETH in Milan, Italy and Zurich, Switzerland, respectively. Ms. Elgani recently completed her Ph.D. at ARCES in Bologna, Italy and her main research interests include low-power Analog circuitry for the IoT.



10:50 - 11:10

PCM Memory IP in 90nm Smart Power

The development of 90nm Smart Power BCD technology including Phase Change Memory (PCM) is an important milestone for ST Microelectronics and for the new product definition. The memory design, verification and silicon validation within R3-PowerUp Project, starts from PCM bit-cell and related Technology Qualification Vehicle implementation to the actual design of target Memory IP for a BLDC motor driver prototype for automotive application. This talk will provide an overview of the design solution considered to achieve a robust and reliable PCM memory able to cycle up to 100k writes and able to cope from -40C up to 175C the operation requirements. A specific Error Correction Code and temperature compensation write mechanism are exploited also granting the target product performance for speed and power consumption.


Marcella Carissimi (STMicroelectronics, IT)

Marcella Carissimi received the Laura Engineering Degree (Laude) in electronic engineering from Politecnico of Milano, Italy. She joined STMicroelectronics in 2001 and she has been involved in the design of Flash memory and Cost Effective NVM solution. Since 2015 she leads the project of embedded PCM memory design for BCD technology for consumer and automotive product in 90nm, and her research interest is about A-IMC on PCM memory in 28nm.

11:10 - 11:30

Hall-effect sensors in BCD10

BCD is a key technology for smart power ICs since it enables coexistence on the same chip of low-voltage control circuits and high-voltage DMOS stages. Galvanically isolated current sensors, such as Hall-effect sensors, are fundamental in many power circuits: they can be used in the control loop as well as in safety protection circuits. This talk will discuss the main challenges in the implementation of Hall-effect current sensors in BCD technology, with a specific focus on the realization of broadband current sensors.


Marco Crescentini (ARCES-University of Bologna, IT)

Marco Crescentini (M’10) received the Dr.Eng. degree (cum laude) in electronic engineering and the Ph.D. degree in information and technologies from the University of Bologna, Bologna, Italy, in 2008 and 2012, respectively. In 2009, he joined Infineon Technologies, Villach, Austria, as an intern, focusing on the performance analysis of dc–dc converters. Since 2016, he has been a Researcher/Assistant Professor of instrumentation and measurement with the Department of Electrical, Electronic and Information Engineering “Guglielmo Marconi”, Cesena Campus, University of Bologna, Italy. He is a scientific member of the joint laboratory between STMicroelectronics and University of Bologna. His current research interests include the design of high-accuracy, low-noise, and broadband instrumentation for either biomedical or energy applications. Dr. Crescentini has authored/coauthored more than 40 peer-reviewed journal/conference technical papers and 3 international patents. He is a member of the IEEE SSCS and I&M societies, and of the Italian Association of Electrical and Electronic Measurement



11:30 - 11:50

TCAD predictions of hot-electron injection in p-type LDMOS transistors

One of the major issues concerning the design of rugged power LDMOS devices to be integrated in next future BCD technologies comes out to be the prediction of the physical mechanisms in the high-field regime, such as impact-ionization, hot-carrier degradation and oxide hot-carrier injection in order to accurately address their performance along with their long-term reliability. This is mostly true for the p-channel LDMOS devices. To this purpose, the hole impact-ionization coefficient and the hot-electron injection model presently available in the Synopsys TCAD tool have been calibrated on ad-hoc test structures and validated against a state-of-art p-channel power LDMOS device featuring the STI architecture. The study has been extended to extremely high electric fields, as expected in new-generation power LDMOS, adopting the deterministic solution of the Boltzmann equation to accurately capture such effects.


Federico Giuliano (ARCES-University of Bologna, IT)

Federico Giuliano received the M.S. degree in Physics from the University of Bologna, Italy, in 2017. He is currently pursuing the Ph.D. degree in electronics, telecommunications and information technologies with the Department of Electronics (DEI) at the University of Bologna.

He is currently with the Advanced Research Center for Electronic Systems (ARCES), University of Bologna. His main research interests include the physical modeling and numerical simulations of high-power devices.

11:50 - 12:00




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