IPCEI Workshop
Monday 19 September 2022

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IPCEI Workshop

(Room - 16) Half day

08:30 - 12:00

Chair

Angelo Messina (STmicroelectronics, IT) 

Angelo Alberto Messina received his M.Sc. Electronics Engineer Degree in 1997 from the University of Catania and after he got his Ph.D. in “Advanced Technologies for the Photonics and the Optoelectronics and Electromagnetic Modeling” and a M.Sc. Degree in Physics from the University of Messina where he worked four years in the research team of the “Physics of Matter and Electronic Engineer” Department. He is, from 23 years, in STMicroelectronics Company working now in R&D and Public Affairs Dept. being portfolio manager of several European Research Projects/Programs.

Overview 

In December 2018 the EU Commission approved a project proposal of four EU member states (France, Germany, Italy and the UK) to start an Important Project of Common European Interest (IPCEI) on Microelectronics. Those Member States have been joined by Austria in 2020. The IPCEI-ME initiative enables the first industrial deployment of innovative microelectronics products and steers research, development and innovation efforts towards new emerging downstream markets (e.g. Automotive, Industry 4.0, IoT). Among the project’s overall technical objectives: semiconductor chip technologies, integrated circuits, sensors, assembly and packaging technologies as well as advanced equipment and materials. The IPCEI-ME is focusing on five technology fields: 1.Energy efficient chips 2.Power semiconductors 3.Smart sensors 4.Advanced optical equipment .5.Compound materials. The goal of the workshop is to present recent results of key IPCEI-ME partners to the European semiconductor community, industry representatives and RTOs.

08:30 - 08:50

Robust Packages for Pressure Sensors

Pressure sensors require a pressure port, i. e. a channel connecting the actual MEMS sensor structure on the chip
with the environment. This channel makes the sensor “feel” the external pressure, but at the same time it enables
all kinds of environmental substances to somehow deteriorate chip and sensor functionality. Obviously, reliability
requirements are application specific. The presentation lists several package options and measures on how to
establish application-specific robustness levels. In the 2nd part of the talk we elaborate on another MEMS-specific package challenge, which is the sensitivity to mechanical stress/strain. Semiconductor packages always induce stress onto the die. This mechanical load creates parasitic sensor signals and thus must be minimized. We compare approaches and measures on how to achieve low stress chip environments. The focus of the presentation will be on 1st level packaging, but we will still briefly discuss the overall value chain from wafer fab to module.

Speaker

Horst Theuss (Infineon, DE) 

1993: PhD in Physics, University of Stuttgart, Germany
Max-Planck-Institute for Metal Research, Stuttgart, Research staff
1994-1995: IBM Almaden Research Center, San Jose, CA - Postdoc
1996-2000: Vacuumschmelze Hanau, Germany – Product Marketing Mgr.
2000-2022: Infineon Technologies AG, Regensburg Germany
As a Senior Principal he is today responsible for predevelopments focusing on new packages for MEMS and Sensors.

08:50 - 09:10

Silicon photonics enrolled for chip-to-chip interconnects and consumer applications

Silicon photonics is a CMOS based solution on SOI substrates enabling the interface between electrical modulation and optical links. With the recent evolution, this technology becomes available for many other applications beyond datacenter transceivers. Foundries and design kits are ready in 8 and 12" wafers.

Consumer applications and chip to chip interconnect are adopting this solution. High performance computing and Ai would give a large leverage for the CMOS industry with co-package optics.

The presentation is introducing the silicon photonics technology with the substrates requirements and its enhanced features enabling better performances for applications.

Speaker

Alain Delpy (Soitec, FR)

Alain Delpy’s microelectronics experience ranges from design through marketing in the areas of industrial and consumer applications. Today his primary focus is  on silicon photonics development for various applications with a main driver on emerging innovation using SOI or other substrates.
He joined Soitec in 2018 as Business Development Manager for the Smart division. His focus has been bridging Soitec’s substrate engineering with the market needs to partnering and creating innovative applications
Prior to Soitec, Alain joined the technology industry and in particular STMicroelectronics where he focused on communications devices and applications. Later on he moved to the imaging area for camera applications.

09:10 - 09:30

22FDSOI device millimeter-wave characterization (up to 110 GHz and beyond)

Marching into 5G communication era, it poses opportunities and challenges on the semiconductor industrial. The device characterization including small-signal and large-signal behaviors in mmWave frequency becomes vital to the success of the mmWave application. In this talk, small-signal analysis on a small-signal analyses on a variety of 22FDSOI device up to 110 GHz. A methodology of on-wafer calibration beyond 110GHz will be discussed. To facilitate low noise amplifier (LNA) design, the RF noise performance of 22FDSOI core devices in mmWave frequency range will be demonstrated. Large-signal characterization and modeling are also important for power amplifier (PA) design. Since PA is normally operated in large power, thus, the behavior after RF power stress is of interest for manufacture. In this talk, the RF reliability results will be presented as well.

Speaker

Zhixing Zhao (GlobalFoundries, DE) 

1993: PhD in Physics, University of Stuttgart, Germany2020: PhD in Electrical Engineering, University of Calgary, Canada

2015-2016: Internship as a RF Engineer in IBM/GlobalFoundries in Burlington
2017-2022: GlobalFoundries, Dresden, Germany
Zhixing works as a device engineer in GlobalFoundries and focuses on RF/mmWave device development on 22FDX technology.

09:30 - 09:50

High-NA EUV Optics: preparing the next major lithography step

For more than 50 years, Moore's Law has been driven by resolution improvements of lithography scanners which generate an image of the lithography mask on the semiconductor wafer. This image contains the patterning information needed to build up an integrated circuit. The latest scanner generation uses 13.5 nm light (EUV) at 0.33 NA and is now essential to produce leading edge semiconductor devices. To further increase the resolution ZEISS is working on next generation EUV optics. These consist of a highly flexible illumination system and 0.55 NA projection optics, enabling single-exposure sub 8nm half-pitch resolution. Here we explain the system design of the high-NA optical column and report on the manufacturing status of mirrors and frames. Furthermore, the buildup of the infrastructure including mirror polishing, coating, surface figure metrology, mirror handling, and integration tooling are shown.

Speaker

Alexandre Lopes (Zeiss, DE) 

2015: PhD in Physics at the University of Freiburg, Germany
2015-2019: R&D engineer and team leader at several DUV and EUV projects at Carl Zeiss SMT
Since 2019: Key Functional Systems Engineer in ZEISS High-NA Mirror Metrology

09:50 - 10:10

IPCEI contribution to energy efficient Si and SiC based solutions for e-mobility

Infineon is known to provide technologies, which are strongly supporting Europe’s efforts to cope with the challenges of climate change. Traditionally, Infineon’s energy efficient solutions help to reduce the CO2 emission and are enablers for the successful technological transformation of our society.

In the context of IPCEI ME, Infineon Austria is working on the development and ramp up of leading edge products for different applications. Subject of this presentation will be the introduction to Si and SiC based technologies for energy efficiency and their application in e-mobility.

Speaker

Martin Mischtz (Infineon, AT) 

1996: PhD in Chemical Technology, Graz University of Technology, Austria

1996 - 2000: R&D engineer in chemical industry (e.g. HOECHTS, NOVARTIS)

since 2000:  Infineon Technologies Austria, Villach, Austria

2000 – 2006: R&D engineer in semiconductor production

2006 - 2008: Project manager for continuous improvements in production 

2008 – 2019: Group leader and project manager for innovation (new materials, additive manufacturing) 

2019 - 2021: Manager for innovation and funding in national and European funding projects

Since 2021: Coordinator of all IPCEI ME activities of Infineon Austria

10:10 - 10:40 Coffee Break

10:40 - 11:00

Experimental and numeric methodology for characterization of SiC power module

Silicon carbide (SiC) power modules are currently spreading in automotive market thanks to the superior electric
and thermal properties of SiC devices with respect than their silicon counterparts. This technology improves vehicle performance and efficiency, employing at the same time more compact electric components and a lighter battery pack. Nevertheless, SiC power module shall be able to fully exploit device capability during the entire product mission profile. In this contribution, an overview of reliability concerns related to SiC power module is provided. Then, some experimental and numerical methodologies, aimed to optimize this aspect, are presented. These techniques analyze different physical domain (electric, thermal, mechanical) and can give support during the entire product development.

Speakers

Alessandro Sitta (STMicroelectronics, IT) 

Alessandro Sitta received the M.S. degree in mechanical engineering and the Ph.D. degree in system, energetic, computer and telecommunication engineering from the University of Catania, Italy, in 2016 and 2021, respectively. Since 2017, he has been a Research Engineer with the Automotive and Discrete Group, Research and Development Department, STMicroelectronics, Catania, Italy. His research interests include power semiconductor device thermomechanical modeling, reliability estimation, and material and device experimental
characterization.

Angelo Alberto Messina (STMicroelectronics, IT
Angelo Alberto Messina received his M.Sc. Electronics Engineer Degree in 1997 from the University of Catania and after he got his Ph.D. in “Advanced Technologies for the Photonics and the Optoelectronics and Electromagnetic Modeling” and a M.Sc. Degree in Physics from the University of Messina where he worked four years in the research team of the “Physics of Matter and Electronic Engineer” Department. He is, from 23 years, in STMicroelectronics Company working now in R&D and Public Affairs Dept. being portfolio manager of several European Research Projects/Programs.

11:00 - 11:20

Analog Virtual Testing

Silicon testing must be done fast and reliable. Test program debug can only start when silicon is in house. Test Program development is labor intensive and should start as early as possible. This is a challenge because the real design will be only available just before tape out. Analog virtual testing is a novel way to enable test program development earlier in the design phase. Enabling early test program development is an organizational challenge. However enabling the Test Engineer to understand and develop the test program in parallel to DUT design is of paramount importance for successful product development. Behavioral models (wreal) for the analog parts of the SOC together with RTL enable fast simulation of the chip functionality. The gap to connect the test program into the simulation environment had to be closed . Test requirements have been defined by using a machine readable test language called bitfield scripts. These can be simulated upfront in the existing verification environment. A way to simulate the test program source code with the modelled DUT was developed. Therefore analog states and digital patterns can be simulated before silicon is available, guaranteeing a fast bring up. This work has been caried out under the umbrella of IPCEI by the development of an UWB Transceiver.

Speaker

Boris Müller (NXP Semiconductors, AT)

Boris Mueller (male) was born in Freiburg, Germany, in 1979. He holds a Master’s degree in Electrical Engineering and Audio Engineering(Dipl.-Ing.) from the Technical University of Graz. After working in the field of acoustics and sound reinforcement for several years he joined NXP Semiconductors to focus on the second part of his professional career. He started in 2012 as a contractor and became an expert in behavioral modelling. In 2016 with the establishment of the modelling team he became a full-time employee. Since 2017, Boris Mueller is involved in RF & LF automotive R&D projects, working as integrator and modelling engineer.
Dennis Jeurissen (male) studied (1995-1999) at the Poly Technic “Fontys” in Eindhoven (Netherlands) and graduated in 1999 started at Philips research in February 2000. He worked as Research engineer in the integrated Transceiver team exploring RF systems in deep-sub micron technologies ranging from 180nm – 45 nm. The integrated circuits he worked on consist of one chip TV tuner (bicmos), bluetooth (CMOS18), WLAN (CMOS065), Software Defined Radio (CMOS045) and Satellite Radio(CMOS065). In 2010 Dennis relocated to Austria and became the analog team lead in the PL Secure Car Access of the BL Advanced Analog. There he developed with the team an UHF RF CMOS Transceiver (CMOS14) operating in the ISM band for Automotive applications. Since 2013 Dennis became the manager of the Physical design and Design for Test team. In 2015 he also started a behavior modelling team. The Analog Mixed Signal products which are designed in this PL are manufactured in 140nm – 28nm technology.

11:20 - 11:40

SiC Switches at Bosch for Automotive Propulsion: Ramp-Up for First Industrial Deployment

In this contribution, we present our activities on Silicon Carbide (SiC) MOSFETs to enable a sustainable automotive propulsion technology. This includes a benchmark of our dual channel trench gate technology against the market technologies based on RdsA. Furthermore, we will motivate by discussing physical material parameters, the challenges associated to 4H-SiC (with respect to Si) to outline the “ramp-up dynamics” related to industrializing automotive quality. Finally, we acknowledge the IPCEI funding for our SiC pilot line that helped us to realize our targets.

Speaker

Holger Bartolf (Bosch, DE)

Holger Bartolf received his Dipl-Phys. and Ph.D. degree from the Karlsruhe Institute of Technology (KIT) and the University of Zurich, respectively. He developed nanotechnology on the 10nm lengthscale capable of cryogenic singlephoton detection. In 2011 he joined ABB Corporate Research, where he developped SiC rectifiers and supervised the 1st SiC MOSFET technology prototypes for 3.3kV traction applications. Since 2016, he works as a SiC FET design engineer at Robert Bosch GmbH in Reutlingen. To elucidate the interest on power device design and nanotechnology in the next generation of engineers, he gives lectures at the University of Stuttgart (EEPSAT).

11:40 - 12:00

New generation of power electronics module packaging

Power electronics module packaging is becoming of great importance. Low parasitic effects and heat dissipation are crucial. In this contribution we introduce into the new power electronics module packaging developed at AT&S.

Speaker

Hannes Stahr (AT&S, AT) 

Hannes Stahr received the DI degree from the University in Graz in 1988, where he studied electronics and telecommunication engineering. He works as a Fellow in AT&S and was deeply involved in the most recent developments for HDI PCB. Since 1997 his focus area is component embedding in PCB starting with printed passive components. In 2008 he guided the FP7 project Hermes to success which resulted in the industrialization of the chip embedding technology and later to the foundation of the business unit Advanced Packaging in AT&S. In 2013 he guided the Catrene project EmPower for embedding of power semiconductors and the development of power modules with double sided cooling. He is involved in the development of new embedding concepts to enable high density fan out for high power computing for autonomous driving. In 2020 the ECSEL project CHARM was started to support this development. He is author and co-author in over 20 filed patent families for PCB and advanced packaging.

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