Workshops and Tutorials
Monday 19 September 2022
Future of Short Reach Interconnect
Davide Tonietto (Huawei Technologies, CA)
Davide Tonietto graduated in Electrical Engineering from Pavia University, Italy in 1996. He has worked in several IC companies as analog IC designer and technical manager. He holds more than 20 US patents in the areas of Analog and Mixed Signal IC design and wireline communication systems and authored several papers on the subjects. He joined Huawei Canada in 2011 where he is currently Huawei Fellow and Senior Director. He founded and leads Hisilicon Serial Link (HiLink) a global organization based in Canada and China which supplies Hisilicon with a complete SerDes IP platform targeting all Huawei products and applications: Networking, Datacenter, HPC, Wireless Infrastructure, Mobile & Consumer.
His research interests are in the areas of SerDes architecture, design, optimization and testing. He is currently involved in the definition of the technology roadmap for Near Package and Co- Packaged Optics (CPO and NPO).
The unprecedented information explosion and its exponentially increasing demands on data traffic and processing are pushing a rapid and diverse evolution in short reach interconnect technologies. In the background of this race, CMOS technology is not providing the usual node over node boost in performance to help SerDes designers cope with higher bandwidth and data rates. Breakthroughs in high speed electrical interconnect and new approaches in optical interconnect, such SiPho, NPO (near package optics) and CPO (co-packaged optics) promise improved performance, energy efficiency and density. How are these new technologies going to address the ever more complex power and density problems facing our industry? What are the specific challenges that new and emerging applications such as AI and HPC are posing on interconnect? How interconnect technologies are going to respond to the need for die disaggregation and multi-die IC products? Is a Chiplet IC ecosystem around the corner? Presenters will touch on key technologies that are needed to face these challenges as well the overall vision of the industry trends and needs, broken down to market areas (traditional routing/switching, transport, DC, AI, HPC).
- Limits of electrical channel, new passive channel technologies & and signaling
- Coding, error correction, error mitigation, error prediction
- Novel architectures and design techniques for 100 Gbps and beyond
- Serial links for emerging applications: AI, Computing and Automotive
- High density embedded photonics: Sipho, monolithic vs. non monolithic photonic, linear vs. retimed CPO, NPO, AOC
- Interconnect from the packaging and assembly technology: 2.5, 3D, multi-die assembly
- ML applied to channel & circuit optimization
08:30 - 08.40
Welcome and introduction
08:40 - 09.20
The Roaring 20’s of Ethernet Evolution
The IEEE 802.3 2020 Ethernet Bandwidth Assessment painted an all too familiar picture – based on observed trends and data, Ethernet would need to evolve beyond its current highest rate, 400 Gigabit Ethernet (GbE), to support the future bandwidth requirements of multiple application spaces. After a yearlong study of this bandwidth challenge, the IEEE P802.3df 200 GbE, 400 GbE, 800 GbE, and 1.6 TbE project was defined and is anticipated to be approved by the IEEE this December.
In response to the bandwidth needs of multiple application spaces, the IEEE P802.3df project will be one of the largest projects in recent IEEE 802.3 history. The project will define 800 GbE and 1.6 Terabit Ethernet (TbE). It will also use the technologies developed to support these speeds and apply them to develop lower-cost, higher density solutions for 200 GbE and 400 GbE. In totality the project will define a total of 26 electrical and optical specifications that address a multitude of application spaces from short copper traces on printed circuit boards to copper cables to optical solutions ranging from 50m to 40km. In addition, it is anticipated that specifications will b developed based on either 100 Gb/s and / or 200 Gb/s. In essence, this single project will address a range of specifications in the past that were addressed by a multitude of projects.
Given the breath of specifications being addressed, a holistic approach to the development of the underlying architecture will be employed that will consider the needs of all these specifications simultaneously. The importance of the interaction of the underlying architecture and the forward error correction schemes that will need to be employed cannot be overstated. While addressing the obvious bandwidth requirements, the architecture and physical layer specifications will need to balance the need for flexibility with latency and power constraints.
An update on the status of the IEEE P802.3df project at the time of the presentation will be provided. As the development of the architecture is seen as the first priority of the project, the timing of this presentation in relation to the project is perfect to gain insight into the future of Ethernet.
John D’Ambrosia (Futurewei Technologies, US)
John D’Ambrosia is a Distinguished Engineer at Futurewei Technologies, a U.S. subsidiary of Huawei. John is currently the Acting Chair of the IEEE P802.3df 200 Gb/s, 400 Gb/s , 800 Gb/s and 1.6 Tb/s Task Force. He is also chairing the IEEE P802.3cw Task Forces that is developing 400 Gb/s Ethernet over DWDM systems. Previously, Mr. D’Ambrosia led the IEEE 802.3 task forces that developed 40 Gb/s and 100 Gb/s Ethernet, 200 Gb/s and 400 Gb/s Ethernet, as well as the IEEE 802.3 New Ethernet Applications Ad hoc. John is also a member of the IEEE 802 LMSC Executive Committee and is an IEEE Senior Member. In addition to his multiple roles in IEEE 802, he is an advisor to the European Photonics Industry Consortium and was the Chairman of the Ethernet Alliance from 2011 to 2019. His previous work experience includes Dell, Force10 Networks, and Tyco Electronics.
The future of interconnect from server to Edge Cloud
New technologies are emerging with speeds accelerating from the server to server and the inter-data center connectivity at the Edge. The talk will discuss the next five years of interconnections needs and technologies to deliver the future ultra-high-speed server connectivity, advanced network topologies, and special needs for the Cloud Edge networks. The talk will also discuss the business and operational impact of interconnecting technologies driving for a technology convergence where possible.
The speaker, Mr. Yuval Bachar, with 32 years of experience, is an evangelist in networking and interconnect technologies.
Yuval Bachar (ECL,US)
Yuval Bachar recently started a startup company (ECL). ECL defines a new data center category by democratizing the high-end data center technologies to everyone. ECL is creating a true zero-emission, off-grid colocation and edge solution for the industry.
Before that, Yuval was a principal hardware architect at the Azure Platform; in that capacity, his work focused on data center self-healing leveraging Machine Learning and Artificial Intelligence, predictive maintenance, and hardware quality consistency control at -scale.
Prior to his role at Microsoft, Mr. Bachar was a principal engineer in the global infrastructure and strategy team for Linkedin, responsible for the company strategy for data center
architecture and the mega-scale company data centers. He drove and supported the new technology development, architecture, and collaboration for the 10x compute & storage growth
and 25x network connectivity growth in that capacity. Yuval Bachar was one of the founders and innovators of the Open19 project and president of the Open19 Foundation. As part of this
work, Mr. Bachar was responsible for developing this new community and Open19 technology to support the Open19 Community.Prior to Linkedin, Mr. Bachar was the leader and architect for Facebook data center networking hardware, responsible for developing the Wedge and 6-Pack first top of Rack (ToR) and modular open networking gear. Also, Mr. Bachar was the innovator and driver of the $1/1G optical technology initiative for 100G pluggable modules. Furthermore, he redefined the backbone architecture and integration of colored optics into the switching platforms.
Earlier, Mr. Bachar served as Senior Director of Engineering in the CTO office in the Data Center Group at Cisco, responsible for its data center product portfolio and next-generation innovation. He drove and supported next-generation systems' architecture, product market positioning, and cross-Cisco product alignment in this capacity. Yuval Bachar is also responsible for evangelizing new Edge and IoT technologies and integrating them into the industry and future data centers.
Before this stint at Cisco, Mr. Bachar served as VP/CTO of the High-End Systems Business Unit at Juniper Networks. He drove Juniper's high-end systems architecture, market, and technology positioning in this capacity, including product, technology, and system-level innovation and alignment across the company. Mr. Bachar was also held in a range of roles at
Cisco Systems networks for over 14 years, responsible for system-level architecture, hardware design, and management roles for groups ranging from 5 to 125 people. Before joining Cisco,
Mr. Bachar held various Digital Equipment Corporation (DEC) roles in the semiconductor group.
Mr. Bachar was recognized as a top influencer in the data center industry: Top 50 of data centers in the Americas and Edge data centers globally: 10 Innovators South of the Rack, Top
50 America's data center influencer – 2018, Top 50 Edge influencers 2019, Data Economy 'Power 200' Leaders, iMasons IM100, 2020
Mr. Bachar has been a contributor to the PCI standard and several IEEE standards. He holds eight approved US patents in the data center, networking, system design areas, and three
Cisco pioneer awards. Mr. Bachar has a BSEE from the Technion in Haifa.
10:30 - 11:00
Mind the Gap: Shorter Interconnects for Optimal Latency & Power in Data Center SoCs
Data center SoC architectures are going through a seismic shift due to the need for faster data processing, higher bandwidths with minimum latency, and maximum power efficiency. SoC disaggregation and co-packaged optics placed closer to the SoC are some of the trends driving heterogeneous compute platforms and the need for short-reach interfaces. The semiconductor industry is collaborating to define standards for such interfaces including XSR, XSR+, and VSR to ease the pain. IP providers are delivering interfaces that comply with the standards as well as enable the lowest latency and power while maintaining high throughput.
Keep up with the new data center trends, meet your evolving design requirements for most complex SoCs targeting high-performance computing and networking applications. Access the die-to-die and short-distance chip-to-chip interface technologies that support a migration path for optics from pluggable to near-package to co-packaged and beyond. Learn how to save power, improve performance, and reduce latency while maximizing yield.
Dino Toffolon (Synopys, CA)
Dino Toffolon joined Synopsys in 2002 and is currently Sr. Vice President of Engineering responsible for the Synopsys DesignWare IP Interface PHY product line.
Before joining Synopsys, Dino worked as a Circuit Design Engineer focused on high speed video and baseband communication chips at Gennum Corporation and Cogency Semiconductor.
Dino has 25 years of industry experience and has been issued over 20 patents in the field of high speed circuits and communications. He holds a B.Eng.Mgt in Computer and Electrical Engineering as well as an M.B.A in Finance from McMaster University
11:00 - 11:30
Fundamental Limits of Wireline Electrical Signaling: Challenges and Opportunities
Data rates in wireline electrical signaling have been increasing steadily from around 1Gb/s in 2000 to today's 200Gb/s, and there is already a march towards 400Gb/s. Will there be an 800Gb/s electrical signaling in the next few years? Will we ever surpass the 1Tb/s mark? This talk will review the fundamental limits of signaling to determine how much room is left in the data rate and explore means of reaching there. In this process, we will identify the trade-offs, challenges, and opportunities that lie ahead of us.
Ali Sheikholeslami (University of Toronto, CA)
Ali Sheikholeslami is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto, Canada, with his main research interests in the areas of analog and digital integrated circuits, high-speed signaling, and CMOS Annealing. He has coauthored over 70 journal and conference papers, 10 patents, and a graduate-level textbook entitled Understanding Jitter and Phase Noise. Prof. Sheikholeslami has received numerous teaching awards, including the 2005–2006 Early Career Teaching Award and the 2010 Faculty Teaching Award, both from the Faculty of Applied Science and Engineering at the University of Toronto. He served on the Memory, Technology Directions, and Wireline Subcommittees of the ISSCC in 2001-2004, 2002-2005, and 2007-2013, respectively. He currently serves as the Education Chair for ISSCC and the Vice President, Education, for the Solid-State Circuits Society (SSCS). He was an SSCS Distinguished Lecturer in 2018-2019. He is an Associate Editor for the IEEE Solid-State Circuits Magazine, in which he has a regular column entitled “Circuit Intuitions”. He was an Associate Editor for the IEEE Transactions on Circuits and Systems — Part I: Regular Papers from 2010 to 2012, and the Program Chair for the 2004 IEEE ISMVL. He is a registered Professional Engineer in Ontario, Canada.
11:30 - 12:00
Burst of errors generation, detection, and correction in modern wireline links
Burst of errors in modern wireline links degrade FEC performance. Error bursts can be induced by clock jitter, supply noise, or the more familiar DFE error propagation and can be classified into two types: Type1, challenging to characterize, is induced by timing perturbations that cause misalignment of clock and data at the receiver ADC and results in a burst that momentarily exceeds FEC’s correction capability. Type2 is induced by DFE and can be described by a Markov chain model. Bursts of errors in practice are a mixture of these two types. This paper first discusses occurrence of error bursts using measured data from a 7nm 112Gbps SerDes. Statistics are also collected under different conditions to further reveal the impact. The paper then discusses special error-correction techniques that can be applied for both types of bursts to improve pre-FEC and post-FEC performances. Also, a novel EoB/SoB/MLSE technique that can save considerable power and chip area is addressed in this paper.
Henry Wong (Huawei Technologies, CA)
Henry Wong received both his B.A.Sc. and Ph.D. degrees in electrical engineering. He has worked for Nortel, Cadence, and Lucent on high-speed coherent modulation and demodulation design, and for Gennum (Semtech) on equalizers, CDR, and SerDes from 2004 to 2013. From 2013 to present, he is at Huawei, Canada for SerDes IP development from 56G to 224G in the role currently as a Distinguished Engineer. He is also a senior manager in DSP development & chip-level system architecture in Huawei. His R&D interest is in power-efficient SerDes transceiver design for backplane and optical engine communications.
Hossein Shakiba (Huawei Technologies, CA)
Hossein Shakiba received his B.Sc. and M.Sc. degrees in Electrical Engineering from the Department of Electrical and Computer Engineering at the Isfahan University of Technology, Iran, in 1985 and 1989, respectively, and his Ph.D. degree in Electrical Engineering from the Department of Electrical and Computer Engineering at the University of Toronto, Canada, in 1997. He has over 35 years of teaching, research, design, and management experience in the area of analog circuit and system design for various applications with focus on wireline communication in both the industry and academia. He is currently working on system and circuit development for next generation serial links at Huawei Canada in collaboration with the wireline industry with emphasis on link design, modeling, and analysis including statistical and signal integrity. He is also actively involved in conducting research with various universities and co-supervises several graduate students.
Yu-Chun Lu (Huawei Technologies, CA)
Yu-Chun Lu joined Huawei Technologies in 2010 as a research engineer. He has been working on the high speed link architecture and modeling and FEC algorithm. He received his B.Eng. degree in communication engineering in 2005 and Ph.D. degree in communication and information system in 2010, both from Beijing Jiaotong University, China. He was a visiting researcher from January 2007 to August 2008 at McMaster University, Canada. His current interests include equalization, CDR, FEC, modeling and simulation methodology of high speed optical and electrical links. Currently, he is working on 224Gbps technologies for optical and electrical links and next generation Ethernet.
13:30 - 14:15
High-Speed Electrical and Optical Transceivers for Emerging High-Performance Computing (HPC) Systems.
Driven by AI applications and increasingly demanding data-processing complexity, throughput, and latency requirements, high-performance computing (HPC) systems continue to evolve. In addition to scaling out processing nodes and increasing number of cores in each node, emerging architectures such as domain-specific acceleration and disaggregation of memory and storage are being deployed. Various kinds of high-speed transceivers are being developed to support both proprietary (e.g., custom XSR/die-to-die) and standard interfaces (e.g., PCIE/CXL) at all levels of hardware hierarchy in these systems, including die-to-die within package, between package devices on the board, board-to-board, and between clusters of boards. In addition to electrical transceivers, co-packaged and 3D-integrated optical transceivers also play key roles in the emerging and future HPC systems. This presentation covers examples of these electrical and optical transceivers, including design constraints and challenges of building such transceivers.
Yohan Frans (Xilinx Inc, CA)
Yohan Frans received B.S. degree in electrical engineering from Bandung Institute of Technology, Indonesia in 1995 and M.S. degree in electrical engineering from Stanford University, California in 2001. From 2001 to 2012, he was with Rambus Inc. where he worked on high-performance and low-power serial links and memory interfaces as circuit design engineer, circuit architect, and design manager. Since 2012 he has been with Xilinx Inc, San Jose, CA. He is currently leading world-wide engineering teams as VP of Engineering at Xilinx Wired and Wireless Communication Business Unit, developing high-speed wireline transceivers for advanced FPGA. His current interests include high-speed mixed-signal circuit design, serial link architecture, transmitter/receiver design, PLL/DLL, memory interfaces, and low-power circuit architectures. He is currently serving as ISSCC Wireline Sub-committee Chair.
14:15 - 15:00
Automotive High-Speed Data Communication Chip Design for Electrical Channels
In this presentation we will illustrate the trade-offs in the design space of a physical layer (PHY) transceiver for wave-impedance based multi gigabit data transmission under the special conditions of automotive applications like electromagnetic compatibility, electro-static discharge robustness and high ambient temperatures. We will focus on the technical compromises between the main degrees of freedom: the transmit power (or power spectral density), the effort in or sophistication of the channel/cable and the effort in or sophistication of the chip implementation of the PHY transceiver. At the same time, the economic consequences of each of these trade-offs will be touched upon.
Secondly, we will provide an example how a “comprehensively optimal” solution for a set of specific application requirements within this design space has been created by using a systematic approach of communication engineering techniques helped by experiences in the automotive application field.
We will give an overview of the resulting 16Gbps PHY architecture and highlight its capabilities and features.
Finally, we will show how this PHY is capable of providing a well-suited link connection for use-cases like very low latency centralized processing radar systems, communications systems with central baseband antenna signal processing as well as slim UHD cameras and remote image-processing units..
Conrad Zerna (Fraunhofer IIS, DE)
Conrad Zerna has been with Fraunhofer IIS since 2008 as an analog designer, project leader and group manager. He has worked on numerous projects for data transmission from Mbps to several 100 Gbps as well as high-speed Analog-to-Digital converters. Several of these implementations are deployed in the Automotive environment. He is holder of 3+ granted patents for system and circuit aspects of data communication.
Fraunhofer IIS is a co-initiator of the Automotive SerDes Alliance and is driving the specification in the capacity of vice-chair/editor for Technical Committees A and B.
Low-Power Wireline/Optical transceivers for Emerging High-Speed Communications
Low-power wireline/optical integrated circuits have become extremely attractive since they are extensively adopted in high-speed communications, such as local area networks, board-to-board, and data center-to-data centers. Energy-efficient 10-224Gbps/lane links with sophisticated equalizations and modulations are studied, including transimpedance amplifiers, analog front-ends, high-speed drivers, and clock data recovery circuits.
Quan Pan (Southern University of Science and Technlogy, CN)
Quan Pan (S’08–M’14) received his B.S degree in Electrical Engineering (EE) at University of Science and Technology of China (USTC) in 2005, and his Ph.D. degree in Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST) in 2014.
From 2014 to 2018, he was Senior Staff Engineer in one Silicon Valley startup company, working on 400GbE high-speed SerDes. He is now an Assistant Professor at School of Microelectronics, Southern University of Science and Technology since 2018. His research interests include High-speed optical and wireline circuit design.
Dr. Pan has contributed to more than 60 peer-reviewed articles. He was awarded the Pearl River Young Researcher in 2019. He received the 2017 Outstanding Young Author Award of IEEE Circuits and System Society. He serves as an active reviewer for many international journals, including JSSC, TCAS, TVLSI, JLT, PTL, JoS, and et al.
16:00 - 16:30
Optimization Tools for Future Wireline Transceivers
Modern wireline transceivers have transitioned from predominantly RF/analog/mixed-signal designs to complex modems with a large custom DSP. This requires design teams to spend ever-more time and effort architecting the modem and validating signal integrity. Thus, the tedious aspects of low-level circuit design optimization must be automated. Accurate statistical signal integrity analysis and architectural optimization tools must be leveraged to permit architectural design-space exploration. Meanwhile, in the lab and in the field, hundreds (or even thousands) of transceiver parameters must be dynamically co-optimized to ensure time-varying performance demands are robustly met. To enable this, physical-layer transceivers must communicate and co-ordinate autonomously. These needs will continue to grow with shrinking performance margins and the proliferation of modulation and coding formats at 200Gbps and beyond. Fortunately, advanced optimization and machine learning techniques can be leveraged to meet these challenges. Trained software agents can help designers optimize circuits, and can dynamically monitor and adapt transceiver parameters during operation.
Tony Chan Carusone (University of Toronto, CA)
Prof. Tony Chan Carusone has taught and researched integrated circuits and systems at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received seven best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. Prof. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.
16:30 - 17:00
Discussion and Closure