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Workshops and Tutorials
Monday 19 September 2022

BEOL Compatible Ferroelectric Device Technologies for Neuromorphic Computing

(Room - Aula 10)



David Esseni (University of Udine, IT)

Stefan Slesazeck (NaMLab, DE)

David Esseni is a professor of electronics at the University of Udine, Italy. During year 2000 he was a visiting scientist at Bell Labs - Lucent Technologies, Murray Hill (NJ-USA), and in year 2013 he was a visiting professor at University of Notre Dame (IN-USA) supported by a Fulbright Fellowship. D.Esseni is the author of numerous papers and of six book chapters about the physics, operation and design of solid state devices, and about the exploitation of emerging technologies in CMOS integrated circuits. He has been frequently invited to deliver presentations at international conferences. He is co-author of the book "Nanoscale MOS transistors: Semi-classical transport and applications" (Cambridge University Press, Cambridge (UK), 2011.
D.Esseni is Fellow of the IEEE Electron Devices Society, and he has been Associate Editor of IEEE Transactions on Electron Devices from 2008 to 2017, as well as Guest Editor of a few Special Issues of the same journal. D.Esseni has served or is serving as a member of the technical committees in several conferences including IEDM, IRPS, ESSDERC, SISPAD. He was the General Chair of SISPAD 2019. He has been PI for his institute of several research projects funded by the European Union and by the Italian MUR, as well as of industry funded projects.

Dr.-Ing. Stefan Slesazeck received the Ph.D. degree from TU Dresden in 2004. Since 2009 he is a Senior Scientist with NaMLab responsible for concept evaluation, hardware development, electrical characterization, and modeling of memories. On these topics, he is (co)-author of >200 publications and holds 6 US patents. His research interests comprise the development of novel memory devices with a focus on ferroelectric devices such as FeFETs and FTJs as well as research on novel computing paradigms based on these devices. Prior to joining NaMLab Stefan was a project leader for the predevelopment of new memory concepts with Qimonda, Dresden, Germany, focusing on concept evaluation for 1T-DRAM, including floating body devices, cell concepts, and access schemes for WL-driver and sense amplifier. As a Device Engineer with Infineon Technologies, he focused on the module  development of 3D DRAM access devices in 65-nm and 46-nm buried word line technology and predevelopment of 3D DRAM access devices.


In the year 2020 the BeFerroSynaptic project was formed among 12 partners from 6 European countries, funded by the European Commission. The scientists from industry and academia work together, combining their expertise in CMOS chip manufacturing and integration (XFAB, CEA), material and device development (NCSRD, IBM, HZB, NaMLab, TUD), simulation and modelling (UNIUD,UNIMORE, ETH) as well as circuit design (UZH, UG). Our approach is to expand the efficiency of conventional CMOS technologies by adding new functionalities of non-volatile ferroelectric memory devices into conventional CMOS logic technologies, that allow to store and to process the data locally (i.e. where it is produced) and by the adoption of neuro inspired architectures. 
Unlike the conventional von Neumann architecture, that uses digital numbers for calculation, in our spiking neural networks the information is represented by event driven and correlated voltage spikes. In the BeFerroSynaptic project we focus on the development of two memory device concepts that utilize the ferroelectric polarization hysteresis to store the information - namely ferroelectric tunnelling junctions (FTJ) and ferroelectric field effect transistors (FeFET). These tiny devices based on ferroelectric hafnium oxide are integrated on top of modern CMOS circuits, directly into the metallization levels of the back-end-of-line process. The ultimate state of expansion of our approach is reached, where both logic and memory functionality of our ‘ferrosynaptic’ devices become synergized together in one synaptic unit.
In this workshop we will shed some light on the different aspects of developments that are mandatory to realize the ferrosynaptic technology, ranging all the way from ferroelectric material and device development, characterization and modelling, circuit and system design towards the realization of fully hybrid integration of FeFETs and FTJs into the BEOL of CMOS chips. In four distinct talks, experts out of the BeFerroSynaptic consortium will introduce the basic concepts and will detail the current development stage of the ‘ferrosynaptic’ technology. Moreover, four invited external speakers will complement the presentations by sharing their broader view on beyond von-Neumann computing, thus revealing how the ferrosynaptic approach arranges within this exciting field.

08:30 - 08.35

Welcome and introduction

08:35 - 09.20

Status and challenges of in-memory computing with emerging memory arrays

In-memory computing (IMC) is receiving strong interest in view of the suppressed data movement, which allows to overcome the infamous memory bottleneck of conventional von Neumann architectures. While IMC has been shown to accelerate deep neural networks and linear algebra operations with several orders of magnitude improvement of energy efficiency, there are still several key issues that should be addressed. At the device level, the most relevant challenge is the statistical variability, which impacts the computing accuracy. At circuit level, a key issue is the IR drop, which must be minimized for improved array scalability by lowering the device conductance. Finally, there are considerable concerns about the overall design approach, where the analog IMC engines must seamlessly combine with the digital processing by smooth data flow and minimized overhead of ADC/DAC circuits.
This talk summarizes the main opportunities and challenges of IMC with emerging memories, providing a benchmarking of the device technologies and a definition of the criteria for ideal computational memory devices. Solutions for variability and IR drop will be shown in terms of programming algorithms and circuit architecture, including redundancy, slicing and mirroring of the memory arrays. Statistical modeling approaches that bridge the physical switching model with the IMC circuit performance are presented. Novel devices and structures for scalable IMC are finally discussed.


Daniele Ielmini (Politecnico di Milano, IT)

Daniele Ielmini is a Full Professor at the Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy. He received the Laurea (cum laude) and Ph.D. from Politecnico di Milano in 1995 e 2000, respectively. He held visiting positions at Intel Corporation (2006), Stanford University (2006) and the University of Illinois at Urbana-Champaign (2010). His research interests include non-volatile memories, such as phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM), and novel in-memory computing circuits. He authored/coauthored 15 book chapters, more than 300 papers published in international journals and presented at international conferences, and 8 patents. He has served in several Technical Subcommittees of international conferences, such as IEEE-IEDM (2008-2009, 2017-2018), IEEE-IRPS (2006-2008), IEEE-SISC (2008-2010), INFOS (2011-2021) and IEEE-ISCAS (2016-2022). He is an Associate Editor for IEEE Trans. Nanotechnology and Semiconductor Science and Technology. He received the Intel Outstanding Researcher Award in 2013, the ERC Consolidator Grant in 2014, and the IEEE-EDS Paul Rappaport Award in 2015. He is a Fellow of the IEEE.

09:20 - 10:00

Towards Computers with the efficiency of the Brain -- Status and Challenges

AI models based on deep learning have demonstrated super-human performance for a wide variety of complex tasks - ranging from language translation to protein folding. However, the energy required to optimise some of the state-of-the-art deep learning models on traditional computational systems have been sky-rocketing. In this talk, I will discuss the current status and future challenges in building a new class of brain-inspired computing systems that employ in-memory computing architectures based on beyond-CMOS nanoscale devices. 


Bipin Rajendran (King's College London, GB)

Bipin Rajendran is a Reader in Engineering at King's College London (KCL). His research focuses on building algorithms, devices, and systems for brain-inspired computing. He has co-authored 90 papers in peer-reviewed journals and conferences and has been issued 59 issued U.S. patents. He holds a Ph.D. in Electrical Engineering from Stanford University. 

10:00 -10:30


10:30 -11:15

Hafnia-based Ferroelectric Tunnel Junction memristors for neuromorphic computing technologies

Ferroelectric Tunnel Junction (FTJ) memristors show promise as artificial synapses for low power neuromorphic circuits.    
First, the progress will be reviewed in the field of perovskite and Hafnia based ferroelectrics such as Hf0.5Zr0.5O2 (HZO), considering both double and single- layer gate stack designs. Focus will be given on Metal-Ferroelectric-Semiconductor (MFS)-FTJs where the bottom electrode is a semiconductor. It will be shown that 5 nm-thick HZO based MFS-FTJ behave as analog memristive memories with a number of non-volatile intermediate states exhibiting synaptic plasticity in the form of long-term potentiation and depression. Although the dynamic range Gmax/Gmin of the synaptic conductance weights is moderate and the ON-current is rather low (~ 0.1 pA/um2), the programming and reading voltage of the synaptic devices are below 1V which makes them suitable for ultra-low power in-memory computing. Moreover, the devices show satisfactory endurance and no retention loss of ON, OFF and intermediate states for several hours. The role of the Schottky barrier near the semiconductor/HZO interface for the operation of the memristor will be elucidated.


Athanasios Dimoulas (NCSR DEMOKRITOS, GR)

Dr. Athanasios Dimoulas is Research Director at NCSR-DEMOKRITOS in Athens. He is founder and head of Epitaxy and Surface Science Laboratory (ESSL) of the Institute of Nanoscience and Nanotechnology since 1999 and currently member of the advisor committee for physical sciences of the Greek government. He has been EC Human Capital and Mobility fellow at the university of Groningen, post-doctoral fellow at CALTECH and Research Associate at the University of Maryland. He has been visiting research scientist at IBM-Zurich and he has been appointed as Chair of Excellence at CEA-INAC(IRIG), and U. Grenoble Alpes, France. He has coordinated several collaborative EU projects and has been awarded the ERC advanced and proof of concept grants. He has served as chair of INFOS conference and chair of TPC committees of ESSDERC and IEDM. His current interests include 2D materials, topological materials and Hafnia based ferroelectric memristors for neuromorphic computing technologies.



11:15 - 12:00

Emerging RRAM technologies and devices for bio-inspired computing

Memristive devices have been receiving an increasing interest for a wide range of applications, such as storage class memory, non-volatile logic switch, in-memory and neuromorphic computing. In bio-inspired computing systems, memristive devices hold the great promise of novel and versatile building blocks for hardware neural networks. Among the proposed technologies, resistance switching oxide-based memristors, also named RRAM, are very promising because of low power consumption, fast switching times, scalability down to nm scale and CMOS compatibility. RRAM devices, also depending on the used material systems and programming strategies, allow the engineering of various interesting functionalities for neuromorphic computing, such as analog dynamics response to input stimuli, and controllable stability of the device resistance states over various time scales. Therefore, RRAMs can act as volatile or non-volatile dynamic memory elements mimicking the short/long term plasticity of synapses in nervous system, or even as  stochastic and non-linear elements in neuronal units. In our work we are engineering both analogue non-volatile HfOx-RRAM as synaptic nodes in spiking neural networks and volatile Ag/HfOx or Ag/SiOx devices (also named diffusive memristors) for both synaptic and neuronal implementation in computing schemes able to process spatio-temporal information.  Beside device engineering and characterization, we further analyze how to exploit their properties in hybrid CMOS/RRAM neural networks through system-level simulations based on equation derived from CMOS circuits and real RRAM devices.


Sabina Spiega (CNR-IMM, IT)

Sabina Spiga is Research Director at CNR-IMM (Agrate Brianza, Italy) and her activity is focused on resistive switching memories and memristive devices for neuromorphic computing. S. Spiga is currently PI for CNR of the EU-Horizon-2020 projects NEUROTECH and MeM-Scales, and she is executive editorial board member of the J. Phys D: Applied Physics, and associate editor of Frontiers/ Neuromorphic Engineering.


12:00 -13:30



13:30 - 14:15

Back-End-Of-Line Integration of Synaptic FeFETs for Neuromorphic Hardware

To emulate the biological synaptic plasticity, an analog programming capability of the artificial synapses is required to define the synaptic weight. Three-terminal synaptic weights have the advantage of separating the write process (through the high impedance gate) and the read process (through the channel). Recently, hafnia-based Ferroelectric Field-Effect Transistors (FeFETs) devices implemented on the Front-End-Of-Line (FEOL) were demonstrated as artificial synapses. However, the FEOL integration imposes constraints on the device footprint, and limits the design flexibility. The Back-End-Of-Line (BEOL) integration is advantageous as it supports a larger device area, which in turn leads to a larger number of ferroelectric domains and, hence, an improved analog behavior. 
In this talk, we will first present the development of materials compatible with BEOL integration, in particular the use of techniques allowing crystallization of hafnia in the ferroelectric phase at a moderate thermal budget below 450°C (laser annealing, millisecond-flash lamp annealing). Then, the fabrication of several architectures of BEOL-compatible FeFETs will be presented: back-gated, top-gated or fins FeFETs consisting of a HZO ferroelectric gate in combination with either an amorphous silicon channel, or a transition metal oxide channel (WOx<3).
The device (conductance range, device-to-device variation, footprint) and weight update (linearity, cycle-to-cycle variation, dynamic range, retention) characteristics of the proposed synaptic weights will be benchmarked to state-of-the-art BEOL FeFETs and more broadly to CMOS-compatible technologies. The resistive switching mechanisms will be discussed based on materials characterization analyses.


Laura Bégon-Lours (IBM Research, CH)

Laura Bégon-Lours joined IBM Research (Switzerland) as a Marie-Curie fellow, where she develops ferroelectric synapses. As an ESPCI-PSL engineer, she followed a PhD on ferroelectric field-effects at CNRS-Thales (France). At the MESA+ institute (The Netherlands), she focused on the epitaxial growth of hafnia.


14:15 - 15:00

Modelling and device design options for BEOL-compatible  ferroelectric-based transistors for neuromorphic applications

Advances in neuromorphic computing demand for modelling and simulations of devices capable to satisfy stringent constraints in terms of energy consumption, reliability and dynamic range. The discovery of ferroelectricity in hafnium oxides in the last decade opened new perspectives for ferroelectric transistors for applications as memristors in neuromorphic computing. In this framework, ferroelectric based FETs and FTJs are envisaged to be good candidates for nanoscale electronic synapses given their demonstrated multiple resistance levels and low energy consumption. Moreover, to unleash the potentials of FeFETs as synaptic devices, a Back-End-Of-Line (BEOL) compatible device architecture is in high demand. In fact, the BEOL fabrication of FeFETs right on top of CMOS circuits holds the promise for great advantages in terms of performance and energy dissipation. 
However, despite these attractive features, the dynamics of the polarization switching that determine the device operation are still debated, thus making the modelling and design of BEOL FeFETs and FJTs a stimulating and challenging research topic. For example, the role of the trapped charge into the device appears to be of utmost importance in the polarization switching and stabilization. Traps also affect the interpretation of some measured quantities like the switched ferroelectric charge in non-trivial ways. Moreover, guidelines are needed for the optimal design of the devices and of the biasing schemes necessary to achieve several intermediate resistance states. These and other topics will be addressed in this talk thanks to both commercial and in-house developed TCAD tools.



Daniel Lizzit (University of Udine, IT)

Daniel Lizzit received the Ph.D. degree in Electronic Engineering from the University of Udine, Italy, in 2016 where he worked on the modelling of electron transport in nanoscale MOS transistors with silicon and III-V semiconductors channels. In 2017, he joined the Italian Synchrotron (Elettra Sincrotrone Trieste) where he mainly worked on the growth, structural and electronic characterization of 2D and quasi-2D materials like Graphene and Transition Metal Dichalcogenides grown on different substrates. Since 2020 he is Research Associate at the Polytechnic Department of Engineering and Architecture of the University of Udine (Italy) and his current research interests include ferroelectric materials for neuromorphic computing applications, and the modelling of metal-2D-semiconductor contacts with ab-initio approach.

15:00 -15:30


15:30 - 16:15

Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised Learning with Ferroelectric Synapses

We propose voltage-dependent-synaptic plasticity (VDSP), a novel brain-inspired unsupervised local learning rule for the online implementation of Hebb's plasticity mechanism on non-volatile memory-based synapses. The proposed VDSP learning rule updates the synaptic conductance on the spike of the postsynaptic neuron only, which reduces by a factor of two the number of updates with respect to standard spike-timing-dependent plasticity (STDP). This update depends on the membrane potential of the presynaptic neuron, which is readily available as part of neuron circuit implementation and does not require additional memory and logic for storage and retrieval. Moreover, shorter pulses in the order of nanoseconds are used for programming instead of pulse overlapping of long pulses which is a common practice for implementing STDP on memristors. Experimental data from the characterization of the ferroelectric devices was used to validate the system-level performance of VDSP. We train a single-layer spiking neural network (SNN) for the recognition of handwritten digits and report performance comparable to the state-of-the-art on the MNIST dataset. Interestingly, the learning rule better adapts than STDP to the frequency of input signal and does not require hand-tuning of hyperparameters. The learning mechanism is simpler in terms of circuit implementation, cuts down power consumption and should enable the design of large-scale neuromorphic systems. 


Nikhil Gargh (3IT, IT)

Nikhil Gargh works on engineering memristor-based neuromorphic hardware for edge AI applications as part of a joint doctorate between 3IT, Canada and IEMN, Lille, in collaboration with Aix-Marseille University and the Paris-Saclay University. He graduated from BITS Pilani, India, with a double major in Biological Sciences and Electrical and Electronics Engineering.

16:15 - 17:00

Spike-based local synaptic plasticity models and BEOL compatible ferroelectric devices

Synaptic plasticity is considered to be the basis of learning and memory in the brain. It goes from low level task-specific learning to high level cognition. Understanding the computational foundations of synaptic plasticity is therefore a growing research that inspires progress in the design of autonomous adaptive systems. In that perspective, a large number of brain-inspired learning rules have been modeled and implemented. Locality, a fundamental computational principle of biological synaptic plasticity, is a key requirement for physical implementation of learning rules. In this talk we provide an overview of models and circuits for spike-based local synaptic plasticity. This overview provides the background for presenting our recent work aimed at the implementation of learning systems based on CMOS and BEOL compatible ferroelectric devices.



Elisabetta Chicca (University of Groningen, NL)

Elisabetta Chicca obtained a "Laurea" degree (M.Sc.) in Physics from the University of Rome 1 "La Sapienza", Italy in 1999 with a thesis on CMOS spike-based learning. In 2006 she received a Ph.D. in Natural Science from the Swiss Federal Institute of Technology Zurich (ETHZ, Physics department) and in Neuroscience from the Neuroscience Center Zurich. E. Chicca has carried out her research as a Postdoctoral fellow (2006-2010) and as a Group Leader (2010-2011) at the Institute of Neuroinformatics (University of Zurich and ETH Zurich) working on development of neuromorphic signal processing and sensory systems. 
Between 2011 and 2020 she lead the Neuromorphic Behaving Systems research group at Bielefeld University (Faculty of Technology and Cognitive Interaction Technology Center of Excellence, CITEC). In 2021 she established the Bio-Inspired Circuits and Systems group at the University of Groningen. Her current interests are in the development of CMOS models of cortical circuits for brain-inspired computation, learning in spiking CMOS neural networks and memristive systems, bio-inspired sensing (vision, olfaction, audition, active electrolocation) and motor control.


17:00 - 17:30

Discussion and closure

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