Workshops and Tutorials
Monday 19 September 2022
A Year of Open Source MPWs: Review, Takeaways and Roadmap
(Room - Aula 11)
Dennis Sylvester (University of Michigan, US)
Over 1 Year has passed since the Skywater 130nm PDK has been released. With over 200+ ICs already taped out and thousands chips expected this coming year, the open-source hardware movement is thriving and revolutionizing the semiconductor scene and practices. In addition to new design techniques exploration and tooling methodologies, the benefits of IC democratization are sprouting into very exciting projects. The goal of this workshop is to review the latest achievements and milestones, industry and academia will discuss their vision and roadmap with a focus on their recent open-source tape-outs and silicon results.
08:30 - 08.40
Welcome and introduction
08:40 - 09.10
Democratizing IC Design: The IEEE SSCS PICO Program
Inspired by the possibilities of open-source chip design, the IEEE Solid-State Circuits Society (SSCS) launched its new Platform for IC Design Outreach (PICO) in the summer of 2021. With this program, the SSCS intends to build new international communities that share our excitement about IC innovation and its democratization toward a new wave of global impact. In its first year, the PICO program was focused on supporting the ramp-up of the open-source ecosystem through sponsored IC fabrication runs on SkyWater’s open-source 130 nm-CMOS process. Four shuttle seats were used to support undergraduates and geographical regions that are underrepresented in IC design. Additional six seats were dedicated to an open-source “Chipathon” that ran from July-November 2021. The contest received 61 submissions and a volunteer jury selected 18 teams from 9 different countries. Through a three-month journey with weekly online meetups, these teams collaborated to combine their designs and fill the available silicon real estate with a variety of analog and digital circuits. This presentation will provide an overview of past and ongoing SSCS PICO activities and their broader goals.
Boris Murrmann (Stanford University, US)
Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters, high-speed communication, and machine learning. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS), the Data Converter Subcommittee Chair and Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC), as well as the Technical Program Co-Chair of the tinyML Research Symposium. He currently chairs the IEEE SSCS future directions committee (SSCD), which established the SSCS’ open source ‘PICO’ design contest.
Open-source hardware ecosystem: New Suttles, PDK releases and tools
The open source hardware movement is getting significant attention with new partners and many users joining the club. New possibilities in open source EDA tooling, IC design and PDKs are expected as the community grows. This talk will cover Google's latest updates and planned roadmap for the coming years. An overview of all the exciting projects in the open source world will be shared as well as Google's perspective on enabling the open source IC design world.
Tim 'mithro' Ansell (Google, US)
Tim 'mithro' Ansell is a software engineer at Google and has been developing open source software for 20+ years. Tim has recently started trying to shake things up in the hardware accelerator development ecosystem by removing roadblocks to having a completely open ecosystem. Recently he worked with SkyWater Foundry to release a fully open source, manufacturable PDK for their 130nm process node and is funding a free shuttle program for open source designs. He has also contributed to projects in the open EDA ecosystem like OpenROAD, OpenRAM, Magic and many others.
10:30 - 11:00
ANAlog GENerators: Lessons Learned and Road Ahead
Over the last 5 years, the development of analog generators and the related methodology behind have gained a lot of momentum. The open-source release of BAG (Berkeley Analog Generator) triggered several research institutes and companies to take a closer look into this novel, good-looking, but also wild and mystic animal called “Analog Generator”. In this talk we describe our experiences with using BAG as a starting point for our ANAGEN program. We show real examples in circuits, optimizers, and the most painful step, layout. Furthermore, we describe our view on the shortcomings in today’s approaches, and how open-source initiatives can support broader adoption of analog generator methodologies in the future.
Thomas Brandtner (Infineon Technologies, AT)
Dr. Thomas Brandtner received the Dipl.-Ing. degree in Telematics from the University of Technology Graz, Austria in 1998, and his PhD in electronics from the University Linz, Austria in 2004. He joined Infineon Technologies Austria AG in 2000. H was working as a methodology engineer for the internal chip/package/PCB co-design flow of Infineon covering connectivity entry, physical co-design, parasitic extraction, and electrical simulation in lead frame, laminate, and wafer-level packages. He was manager of the chip/package/PCB co-design methodology group of Infineon from 2011 to 2016, and its technical lead from 2016 to 2021. Since 2021 he is responsible for the development of an “analog generator” methodology focusing on analog soft macro and programmatic analog IP design, targeting at an Infineon in-house solution as well as building up a world-wide open-source community on that topic.
11:00 - 11:30
European joint OS initiative : vision, mission and strategy
In the recent years open-source IC design community gained enormous tracking with Google SkyWater initiative and DARPA ERI. Though initial outcomes are compelling, they are success stories mostly in digital IC design domain. The development and introduction of new disruptive design methodologies especially for analog/MS/RF into universities and industry design flows is worldwide challenge. In addition several emerging open-source point solutions have significant early adoption barrier and their own limitations. This presentation will provide a vision of the joint open-source initiative and present some of the ongoing and planned activities targeting analog/mixed-signal/RF IC design.
Mirjana Videnović-Mišić (Silicon Austria Labs, AT)
Mirjana Videnović-Mišić received the M.Sc. and PhD degree in Electronics and Microelectronics engineering from the University of Novi Sad, Serbia, in 2004 and 2009 respectively. In 2009 she founded the Team for analog and radio frequency integrated circuit design (ICreate) at the University of Novi Sad, Serbia. In 2010 she joined Faculty of Technical Sciences, University of Novi Sad as an assistant professor. In 2014/2015 she was Fulbright Visiting Scholar and from 2015-2018 she was the Marie Currie Individual Global Fellowship recipient. Both fellowships were executed in cooperation with the Berkeley Wireless Research Center, University California at Berkeley. Since 2018 she is working at Silicon Austria Labs, first as Staff Scientist and as of 2021 Principal Scientist –technical lead for domain of programmatic technology agnostic IC designs. Dr. Videnović-Mišić current research interest are analog and millimeter wave frequency integrated circuits for 5G by exploring the benefits and challenges of the new design methodologies.
11:30 - 12:00
OpenRAM / OpenReRAM : Open Source Memory Generation
OpenRAM is an open-source framework for the development of memories with an initial focus on SRAMs and new extensions for ReRAM. OpenRAM provides an application interface for netlist, layout, and characterization to create designs using either open-source or commercial verification and simulation tools. Three tape-outs have been made to date in Skywater 130nm with successful initial silicon verification of the 32-bit 1kbyte dual-port macro on the first tape-out. This macro is also a part of the Caravel test harness. Subsequent tape-outs have included 10 size and port variants within the Caravel user space. More recently, OpenRAM has been extended for alternate control logic interfaces (e.g. asynchronous), extended banking options, and resistive memories.
Matthew Guthaus (University of California Santa Cruz, US)
Matthew Guthaus is a Professor in Computer Science and Engineering at the University of California Santa Cruz. He received his BSE in Computer Engineering and MSE and PhD in Electrical Engineering, all from The University of Michigan. Prof. Guthaus is a Senior Member of ACM and IEEE and a member of IFIP Working Group 10.5. His research interests are in low-power computing and electronic computer-aided design including new circuits, architectures, algorithms, and software to address challenges in modern design flows. Dr. Guthaus is the creator of the OpenRAM memory compiler and has interests in open-source computer-aided design and design flows. Dr. Guthaus is the recipient of a 2011 NSF CAREER award, a 2010 ACM SIGDA Distinguished Service Award, and a 2019 Google Faculty Research Award.
13:30 - 14:00
OpenTitan RoT implementation in the open-source IC realm
Over the course of the Google/Skywater 130nm MPW shuttles program, multiple SoC have been taped out. Being at the forefront of developments driven by both OpenFASoC and OpenROAD projects, we have been pushing Performance/Power/Area (PPA) using both open-source EDA software and hardware co-design. This talk will discuss the latest development and implementation of the Opentitan Root of Trust (RoT) including newly developed building blocks to improve its resilience to side channel attacks and close the gap with state-of-the-art analog and mixed-signal SoCs reported results.
Mehdi Saligane (University of Michigan, US)
Mehdi Saligane is a Research Scientist in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received the M.Sc. and the Ph.D degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016, respectively. He worked at STMicroelectronics, in France, as a Research Engineer from 2010 till 2015, and after completing his Ph.D, he joined the Michigan Integrated Circuits Lab at the University of Michigan. Dr. Saligane’s current research interest are in low-power and energy efficient IC design with a recent focus on open source EDA and analog and mixed-signal IC design automation. He currently serves as a member of the Technical Steering Committee at CHIPS Alliance and as technical member of SSCS’ open source ‘PICO’ design contest.
14:00 - 14:30
Pre-silicon testing of SkyWater MPW designs using co-simulation with Renode and Verilator
The (new) Caravel harness is based on the LiteX SoC generator, which is very well supported by the open source Renode simulation framework, including automated platform description generation.
The harness integrates with the user area using a Wishbone bus, which is also covered by Renode in a co-simulation scenario with Verilator.
Antmicro has been building a reference flow to perform end-to-end testing of MPW designs including the harness running "natively" in Renode and the user area co-simulated in Verilator directly from HDL, including a sample CI setup providing a painless entrypoint to testing your own design.
With this in place, MPW users will have an easy way to introduce end-to-end testing of their design early on in the process, and continue to use this methodology throughout the development cycle (or cycles - if they re-submit their design into further MPWs).
This effort can also help in the debugging and bringup experience in already manufactured MPW designs.
We will walk through the work performed and explain how to use it and how it can be of use to the SkyWater MPW projects and related activities.
Peter Katarzynski (Antmicro, Sweden)
Peter Katarzynski is Engineering Manager and leads the hardware design team at Antmicro. With a M.Sc. in Computer Engineering and a Ph.D. in Computer Science, Peter has been pushing for a software-driven approach to hardware development in industry and academia.
For nearly ten years he has been coordinating the product design and development process at Antmicro and is actively involved in promoting open hardware. His interests include design automation, hardware visualizations, simulation and mixed ASIC design.
Roundtable discussion, open Q&A for all speakers
15:00 - 15:30